In this paper, we report on initial experiments on the feasibility of a circuit design approach that is based on one-hot multi-valued decomposition of a logic netlist. A binary-valued logic netlist would first be decomposed into multi-valued logic nodes (with multi-valued inputs as well as outputs). For an arbitrary multi-valued logic node, this paper presents a circuit and layout design approach. We first synthesize the multi-valued logic node, using multi-valued decision diagrams (MDDs) to represent each output value of the multi-valued logic node. Each such MDD represents a binary valued output function, on one-hot multi-valued inputs. Assuming that the multi-valued logic node has a κ-valued output, then κ such MDDs completely represent the logic of the multi-valued node. Each such MDD is realized using a very regular, compact domino logic based layout structure. We have compared the delay, area, power and power-delay product of our approach with the same logic functionality implemented in standard cells. Averaged over 15 examples, our approach yields a 22% (26%) improvement in delay, 33% (17%) improvement in area, 42% (29%) improvement in power and a 52% (45%) improvement in power-delay product compared to a delay mapped (area mapped) standard cell based realization of the same functionality.
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