首页> 外文会议>European Solid-State Device Research Conference >A silicon photomultiplier with #x003E;30 detection efficiency from 450–750nm and 11.6#x03BC;m pitch NMOS-only pixel with 21.6 fill factor in 130nm CMOS
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A silicon photomultiplier with #x003E;30 detection efficiency from 450–750nm and 11.6#x03BC;m pitch NMOS-only pixel with 21.6 fill factor in 130nm CMOS

机译:具有> 30%检测效率的硅光电倍增芯片,从450-750nm和11.6μm间距的NMOS - 仅具有21.6%的填充因子在130nm cmos中

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A 16×16 Silicon Photomultiplier (SiPM) is reported in a 130nm CMOS imaging technology with a photon detection probability of >30% from 450–750nm. The SiPM demonstrates a 21.6% fill factor with an 11.6μm pitch and 8μm diameter SinglePhoton Avalanche Diodes (SPADs). This is achieved using a new SPAD structure with integrated resistor and capacitor. NMOS-only pixel electronics are used to improve fill factor and to implement an addressable array of SPADs that are isolated from the array and column load. A 1T DRAM in each pixel is implemented to inhibit the output of high dark count rate (DCR) SPADs. The SiPM also achieves: a median DCR of ≈200Hz at 1.2V excess bias; low after pulsing; and a SPAD timing jitter of ≈95ps at 654nm with a column delay of ≈100–200ps.
机译:在130nm CMOS成像技术中报告了16×16硅光电倍增管(SIPM),光子检测概率为450-750nm。 SIPM显示21.6%的填充因子,11.6μm间距和直径为8μm的单光子雪崩二极管(SPAD)。这是使用具有集成电阻和电容器的新的SPAD结构来实现。仅使用NMOS的像素电子器件来改善填充因子,并实现从阵列和列负载隔离的可寻址的SPAD阵列。实现每个像素中的1T DRAM以禁止高暗计数率(DCR)SPAD的输出。 SIPM还达到:中位数DCR为≈2V的偏差。脉冲后低;和654nm的≈95ps的Spad时序抖动,柱延迟为≈100-200ps。

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