Voltage droop is a major reliability concern in nano-scale VLSI designs. Undesirable voltage droop occurs when logic gates in the circuit draw high switching current from the on-chip power supply network, and this problem is exacerbated at high clock frequencies and smaller technology nodes. A consequence of voltage droop is an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, a.k.a. guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling (DVF) is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For DVF to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop at runtime. Several benchmarks from ITC99 and IWLS'05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.
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