Spiking Neural Networks (SNNs) are an information processing paradigm which is inspired by the way the human brain processes information. There has been considerable research reported on dedicated digital hardware for SNNs as summarised in [3]. However, due to the amount of development time, cost, and inflexibility ASICs are not a good choice therefore reconfigurable hardware (FPGAs) offers a better platform for neuro technologists. In this paper an area efficient multiplier-less hardware architecture is proposed for the implementation of an integrate- and-fire SNN model. The proposed architecture is intended for large scale implementation on a single FPGA. A modular design is proposed in order to make it flexible. Synaptic multiplication is performed with a simple AND gate, and pulses from different synapses are added together at different times, replicating the accumulation of synaptic inputs for the membrane potential. In order to introduce non-linearity into the membrane potential a normalized random number is introduced to this state variable. The proposed architecture uses spike trains as an input much like those in real networks. The rest of the paper is organized as follows. Section 2 provides a brief introduction to spiking neurons, section 3 explains the model, section 4 discusses the proposed architecture and in section 5 conclusions are given highlighting possible future extensions.
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