A 2.52 fJ/Conversion-Step 12-bit 154MS/s with 68.78dB SNDR Full Differential SAR ADC with a Novel Capacitor Switching Scheme

摘要

This paper presents a novel merged technique to decrease the total capacitance and increase the speed of the Successive Approximation Register Analog to Digital Converter (SAR ADC) simultaneously. It is notable that, utilizing the proposed method, the total capacitors are reduced about 40% compared to the conventional split one, reliably. This SAR ADC with modified merging and C-2C technique has been designed and simulated in 180nm CMOS process. The ADC shows a Signal-to-Noise-Distortion Ratio (SNDR) of 68.78 dB and an Effective Number of Bits (ENOBs) of 10.77 bits at 154 MS/s, respectively. The proposed ADC consumes$895muext{W}$, resulting in a Figure of Merit (FOM) of 2.52 fJ/conversion-step as well.