A novel circuit topology for clock-gating-cell suitable for subear-threshold designs

摘要

In this paper, a novel circuit topology is presented for Clock gating cell in which the basic parts (gater and latch) are realized with transmission gate. The simple structure and small amount of leakage power make this topology suitable for ultra-low power designs in subear-threshold regions. Circuit simulations and Post-Synthesis simulation results of a simple Clock gated ITC'99 benchmark circuit show considerable improvements in dynamic and leakage power compared to minimum size Clock gating cell in Nangate open cell library while having almost the same driving capability.