A Novel Voltage Clamped Snubber Circuit Topology Suitable for a Multilevel Inverter with Lowered Power Loss Performance

摘要

This paper presents a novel prototype of lowered loss snubber circuit topology suitable for multilevel voltage source-inverters and rectifiers for high-power applications. The reduced power loss characteristics and voltage capability performances of the proposed voltage clamped snubber circuit are evaluated relative to conventional RCD snubber circuits designed for four-level voltage-source inverters using IGBTs on the basis of experimental results.