We address layout generation of on-chip matched capacitors with the high relative accuracy. Our twisted commoncentroid pattern of unit capacitors consider the post-placement routability as well as reduce a systematic mismatch induced by process gradient. We apply this algorithm to the layout design of an SAR-ADC circuit. Compared with the common spiral capacitor array, our generation method (1) produces a similar low capacitance ration mismatch, and moreover (2) a 100% routability can be achieved.
展开▼
