As the VLSI technology advances, delay variations become extremely large. Delay variation properties caused by various variation factors are different. However, the characteristics of delay variations have not been considered in traditional delay models or asynchronous design styles, which have, therefore, suffered large performance overhead. In this paper, we propose the following two methods for designing high performance asynchronous bundled-data transfer circuits based on the Scalable-Delay-Insensitive model; 1) a variation-aware delay cell library which consists of delay cells exhibiting a wide variety of delay variation characteristics for combinational circuits, 2) a selectable delay line in which we can select an appropriate delay line in accordance with dynamic voltage changes. Then, we show some evaluation results for the variation factor K which represents the margin that guarantees the correct operations. As a result, the performance overhead can be reduced more than 30 percents compared to conventional bundled-data transfer circuits.
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