Case Study of Process Variation-Based Domain Partitioning of GPGPUs

摘要

We can unlock higher performance in general purpose graphics processing unit (GPGPU) chips by adhering to local environment conditions while setting a timing (clock) reference. We propose partitioning the GPU chip into smaller independent domains to enable finer control of the chip voltage frequency (V/F) settings. Post silicon (Si) analysis is used to classify the domains as fast, 'typical', or slow. This information is then provided to the system management unit (SMU) to enable the appropriate settings for power optimization. In this paper, we present an initial analysis of power/performance associated with fine-grain domains in GPUs.