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Layout optimization of CMOS Interconnects for Heating, Cooling and Improved Stress Distribution

机译:CMOS互连的布局优化,用于加热,冷却和改进应力分布

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The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors. First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement. The simulations of the distribution of the temperature and the mechanical stress illustrates the important parameters and their interactions. The paper presents new ANSYS?-simulations on some exemplary heater layout variants in the highly robust metallization design. The scientific questions were the suitability and the benefits of such a heater layout for heating, cooling and stress distribution in CMOS circuits. Different heater-test line models have been analysed by ANSYS?-simulations. The variants of the models were forced or no forced current in heater and/or test line and the kind of metal layer of heater connection. The current density, temperature, their gradients, the hydrostatic stress, the Von Mises stress and the mass flux divergences have been analysed. Such simulations can be utilized to improve parts of circuits like chip corners, sensitive transistors, circuits on GaN-substrate, with TSVs or applications with 3D integration. The local temperature and stress management can be improved by the special metallization layout and the improvement can be supported by simulation data.
机译:CMOS电路的可靠性受电流密度,温度和机械应力的局部不均匀性的影响。由加工和后处理源引起的机械应力,如材料失配,温度阶跃和外在源,如粘合,3D集成和延长的操作条件等于可靠性越来越相关。它可以影响互连的寿命时间性能以及像应力敏感晶体管等有源器件的功能。首先,支持优化互连布局作为提高电路可靠性的特征的开发工作的首先模拟。评估开始于加热器开发用于加速可靠性测试的更高金属层的自加热试验结构。它继续开发高强大的金属堆栈。加热器和高稳健金属化测试结构的模拟和测试证明了这种布局改善的优点。温度分布和机械应力的模拟说明了重要的参数及其相互作用。本文提出了新的ansys - 在高稳健的金属化设计中的一些示例性加热器布局变体上的模拟。科学问题是加热,冷却和压力分布在CMOS电路中的加热器布局的适用性和益处。 ANSYS分析了不同的加热器测试线模型-simulations。模型的变体被强制或者在加热器和/或测试线中没有强制电流和加热器连接的金属层。已经分析了电流密度,温度,梯度,静水胁迫,von误解和质量助焊剂分歧。这种模拟可用于改善芯片角落,敏感晶体管,GaN基板上的电路等电路的部件,具有三维集成的TSV或应用。通过特殊金属化布局可以提高局部温度和应力管理,并且可以通过模拟数据支持改进。

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