The complexity of today's silicon chips is mind-boggling, with over a billion transistors and miles of wires all tightly packed into a finger-tip-sized small area. The key enabling technology for the successful design of these complex chips is the electronic design automation (EDA) software. An important component of EDA is the software responsible for the layout of wires. This talk will focus on the wire routing problem in EDA. We will present challenges and solutions to the problem based on our recent results on wire routing.
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