FPGA Accelerated Parameterized Cache Simulator

摘要

Design space exploration of caches enables the architect to choose the right configuration based on metrics or constraints such as hit rates, power, area, and timing. We propose an FPGA accelerated parameterized two level cache simulator with prefetching using the concept of partial reconfiguration. The key motivation behind the idea is the speed with which the design space exploration can be carried out as compared to software based simulators. This tool can in turn be used to compare the efficacy of results generated by tools such as CACTI, ChampSim and so on. Our tool is expected to report cache metrics such as hit/miss rates for different cache configurations, along with the timing, area and power statistics.