Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors

摘要

In this paper, we propose a powerful AVS-M video decoder that can perform real-time decoding of AVS-M video on embedded RISC processors. Our optimization schemes cover algorithmic improvement, zero skipping, early termination, and data reusing. We have reduced about 90% ～ 93% of complexity after optimization with the proposed techniques as compared to the original reference codes. The proposed low complexity AVS-M video decoder can achieve about QVGA@30fps ～ 50fps when running on ARM920Tprocessor at 384 MHz.