Reduction of IPs energy consumption with ultra-low voltage supply

摘要

In the near future, a number of systems will be powered using energy constrained devices or scavenging technologies, enabling new applications such as medical monitoring, sensors and next-generation portable video gadgets. This will require the electronic circuits to operate with utmost energy efficiency while performing the required functionality. A major opportunity to reduce the energy consumption of digital circuits is to scale supply voltages below 0.4V driving them to sub- (or near-) threshold operation. This workshop presents the expected energy gain and challenges in the ultra-low-voltage (ULV) regime. Our recent ULV achievements will be then described in relation to specific standard cell libraries, adapted CAD margins and Sign-off and ULV digital demonstrators operating down to 0.3V. Last, the enhanced ULV performances offered by the FDSOI28 technology will be highlighted, in relation to an improved ION/IOFF ratio and sub-threshold slope, with promising Silicon results showcased near 0.35V.