This paper presents a modified version of the Selective Fault Tolerance method, which achieves substantial area reduction over the state of the art. This technique is proved to achieve substantial area reduction and better reliability results when applied in conjunction with the so-called SAM method for reliable cache memory. The simulation results show that we achieved an improvement of up to over 20% in terms of area and energy overhead, compared with the state of the art. Also compared to a classic TMR we obtain improvements of up to 65%, with a mean improvement of 25% in terms of area and energy reduction. Furthermore when we combine the simplified selective fault tolerance technique to the SAM method for cache memories and compare the results to a classic TMR, not only we obtain a 65% decrease in area and energy overhead, but also we manage to achieve an improvement in reliability.
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