Design of a High Linear Integrator for Oversampled ADC

摘要

This paper represents a method to enhance the linearity of an integrator by implementing feedback compensation topology. The proposed design reduces signal swing while keeping advantages of both feed-forward as well as feedback topology without changing the signal transfer function. Linearity is related to the output of an integrator. Non-linearity resulted because of the integrator's output swing that is due to change in input. The proposed integrator design when integrated with an oversampled ADC (ΣΔ ADC) significantly increases the linearity. The latch comparator design used to implement first order sigma-delta modulators also discussed. All discussed design is implemented by using 180nm CMOS technology and simulation that verifies the results are given.