Layout Dependent Effects mitigation in current mirrors

摘要

This paper presents a study on how the different physical realization of the transistors constituting a circuit, keeping the same (W/L) ratio, can dramatically alter the circuit specifications, and even functionality. This goes back to the Layout Dependent Effects (LDE), and its effect is increasingly important as the technology scales down into deep sub-micron processes. In this study, different layouts for each building block of an analog circuit, are formulated composing different aspect ratios, and every time the layouts are simulated to see the effect of the extracted views on the schematic results. Different current mirror configurations using a 65nm process are used to show the Shallow Trench Isolation (STI) and Well Proximity Effects (WPE).