65 nm SOI CMOS 60 GHz passive mixer for six-port technology

摘要

This work describes the design and measurements of a 60 GHz passive mixer for six-port applications operating and implemented in a 65nm SOI CMOS technology. The mixer topology, consisting only of a n-MOS cold-FET and CPW transmission line matching networks, avoids the use of coupler in front of the detection circuit commonly found in six-port technology. The simplification reduces the chip size and the power consumption. Demodulation results at 60 GHz are demonstrated to validate the approach proposed.