A 160kGate 4.5kB SRAM H.264 Video Decoder for HDTV Applications

摘要

Observing the design trends in the evolution of multimedia ASIC designs during the past decade, one finds that efficient MPEG-2, MPEG-4, JPEG-2000 encoder/decoder/CODEC designs have been designed with increasing hardware efficiency and lower power consumption. With respect to implementations of MPEG-4 AVC/H.264, there has been one single-chip video encoder [2] and some video decoder cores [3-6] proposed since 2004. This paper presents a low-cost H.264 video decoder for HDTV applications. Compared to a state-of-the-art H.264 video decoder [3], the proposed design can reduce the gate-count by 46% and internal memory by 93% for real-time HD1080 video decoding.