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94 power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone

机译:94 %电源 - 回收和接近零驱动 - 死区N型低丢失调节器,带有20mV的闪存在智能手机中的闪存的短时间负载瞬态

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In power-management integrated circuits (PMIC) for smart phones, cascaded buck and low-dropout (LDO) regulators with N-type power MOSFETs are commonly utilized for high conversion efficiency, power quality and high-density integration as shown in Fig. 27.8.1 [1]. Long paths on printed-circuit board (PCB) from the PMIC to the following applications result in obvious parasitic effects of large LPCB and RPCB, and multilayer ceramic capacitors (MLCC) placed near the application side are necessary. Complex and unpredictable PCB networks induce unexpected poles and zeros in the LDO loop so that an LDO with wide bandwidth (BW) and fast transient response is difficult to design. Furthermore, flash memory, such as universal flash storage (UFS) and embedded-multimedia cards (eMMC), has short-period heavy-to-light-to-heavy (H-L-H) load transients which makes LDO design more challenging. In the waveform shown in Fig. 27.8.1, the gate voltage of the power MOSFET (VGATE) is pulled toward 0V when overshoot of VOUT is caused by a heavy-to-light load transient. Once the light-to-heavy load transient occurs at moment t0 with VOUT overshoot, VOUT then suffers from large undershoot because the N-type power MOSFET has a driving dead zone. The driving dead zone is defined as the region of gate voltage VGATE lower than the VOUT level and the power MOSFET delivers no current. The power MOSFET and compensation capacitance forms a heavy capacitance load so that transient performance is degraded. In prior art, the amplifier (amp) and buffer stage consume large quiescent current (IQ) for easier stability compensation and higher slew rate (SR). In addition, dummy load current (Idummyload) at VOUT or a complex clamping function at VGATE are utilized for the short-period H-L-H load transient of flash memory. However, the efficiency and circuit complexity are sacrificed as a result.
机译:在智能手机的电源管理集成电路(PMIC)中,级联降压和低压丢失(LDO)具有n型功率MOSFET的稳压器,通常用于高转换效率,功率质量和高密度集成,如图27.8所示.1 [1]。从PMIC到以下应用的印刷电路板(PCB)上的长路径导致大型L PCB 和R PCB 和多层陶瓷电容器的明显寄生效应(MLCC )放置在施用方附近是必要的。复杂和不可预测的PCB网络在LDO循环中诱导意外的极点和零,使得具有宽带宽(BW)和快速瞬态响应的LDO难以设计。此外,闪存(如通用闪存(UF)和嵌入式多媒体卡(EMMC))的闪存具有短时间重对较轻(H-L-H)负载瞬态,使LDO设计更具挑战性。在图27中所示的波形中,如图27.1.1所示,当V OUT 的过冲导致v out 引起的电源MOSFET(V 栅极)的栅极电压被拉到0V -to-light负载瞬态。一旦光回重的载荷瞬态发生在时刻t 0 ,v out sumerhoot,v out 然后遭受大的undhoot,因为n -Type功率MOSFET有一个驱动死区。驱动死区定义为栅极电压V 栅极低于V out 电平,并且功率MOSFET提供无电流。功率MOSFET和补偿电容形成重电容负载,从而瞬态性能降低。在现有技术中,放大器(AMP)和缓冲阶段消耗大的静态电流(I <亚> Q ),以便更容易稳定补偿和更高的转换速率(SR)。另外,V OUT 的虚拟负载电流(I dummylad )用于V 栅极的复杂钳位功能,用于短时间HLH负载闪存的瞬态。然而,结果牺牲了效率和电路复杂性。

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