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A high-efficiency and fast-transient digital-low-dropout regulator with the burst mode corresponding to the power-saving modes of DC-DC switching converters

机译:具有与DC-DC开关转换器的省电模式相对应的突发模式的高效率和快速瞬态的数字低压丢失调节器

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Integrated power management (PM) in a system-on-a-chip (SoC) includes a high-efficiency DC-DC switching regulator (SWR) for a high conversion ratio and multiple cascaded digital-low-dropout (DLDO) regulators for post regulation to different functional blocks. Efficient power-saving modes in the SWRs improve the light-load efficiency effectively, e.g. burst mode, skip mode, pulse frequency mode (PFM), and diode emulation mode (DEM) in the constant on-time (COT). Unfortunately, a cascaded DLDO consumes significant power to suppress a large voltage ripple DVSWR from the SWR, even using recent DLDO techniques [1-6], illustrated on the left of Fig. 18.8.1. Overall, the light-load efficiency of the PM seriously decreases. A DLDo with barrel-shifter-based control [1] induces large voltage ripple due to the limiting cycle oscillation (LCO), and the DLDO with freeze mode [2] for power reduction is exposed to large voltage ripples from the SWRs (in power saving modes). The large voltage ripples result in the DLDO frequently switching between the normal and freeze modes and consuming power. The recursive all-digital LDO (RLDO) [3] abruptly changes its control code Q[6:0] due to oscillations between hybrid proportional-derivative successive-approximation recursive (PD-SAR) and pulse width modulation (PWM) duty control, while aVSWR is larger than the pre-defined hysteretic window. In power saving modes, the obvious disadvantage is that state-of-the-art DLDO designs cause extra switching loss and induce large output voltage ripple aVOUT due to large aVSWR. Thus, this paper proposes a DLDO employing a burst mode technique (BMT) to reduce the DVOUT, thereby enhancing the overall light-load efficiency corresponding to the power saving modes in SWRs. The proposed non-linear switch control (NLSC) technique reduces both the number of on/off power switches and varies the switching frequency corresponding to the aVSWR. Moreover, the proposed transient enhance (TE) technique improves transient performance when the DLDO leaves burst mode.
机译:在系统芯片(SoC)的集成电力管理(PM)包括用于高转化率的高效率的DC-DC开关调节器(SWR)和多个级联的数字低压差(DLDO)稳压器用于后调节到不同的功能块。在SWRS高效节能模式有效地提高轻负载效率,如突发模式,跳过模式,脉冲频率模式(PFM),并且在导通时间(COT)的恒定二极管仿真模式(DEM)。不幸的是,级联DLDO消耗显著功率,来抑制大的电压纹波DV <子> SWR 从SWR,即使使用最近DLDO技术[1-6],在左侧图。18.8.1所示。总体而言,PM的轻载效率严重下降。甲DLDO与基于桶形移位器控制[1]诱导大的电压纹波由于限制周期振荡(LCO),与冻结模式[2]为功率减小的DLDO暴露于从SWRS大的电压波动(在功率节能模式)。大电压波动导致DLDO正常和冻结模式和消耗功率之间的频繁切换。递归全数字LDO(RLDO)[3]突然改变其控制代码Q [6:0],因为混合比例 - 微分逐次逼近递归(PD-SAR)和脉冲宽度调制(PWM)占空控制之间振荡,而AV <子> SWR 比预先定义的迟滞窗口大。在省电模式中,明显的缺点是国家的最先进的是DLDO设计导致额外的开关损耗,并诱导大的输出电压纹波AV <子> OUT 由于大的AV <子> SWR 。因此,本文提出了采用突发模式技术(BMT),以减少DV <子>一个DLDO OUT ,从而提高对应于功率节省模式SWRS整体轻负载效率。所提出的非线性开关控制(国家语言服务团)技术减少开/关电源开关的数量和改变对应于该AV <子> SWR 开关频率。此外,提出的瞬态增强(TE)技术改善当DLDO叶突发模式瞬态性能。

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