A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme

摘要

The fractional-N frequency synthesizer is a key building block of wireless systems as it can both generate a high frequency signal with a well-defined frequency and modulate that signal [1,2]. This work addresses two limitations of this architecture; the reliance on analog circuitry in deep submicron technology, and the trade-off between low loop bandwidth for good ΔΣ noise rejection and high loop bandwidth for fast modulation rates. A synthesizer is presented that utilizes an all-digital phase detector in place of the conventional analog-intensive phase detector, charge pump and loop filter blocks. In addition, the design uses a digital dual-modulation scheme that alleviates the trade-off between loop bandwidth and switching speed. These techniques are presented as part of a prototype 14mW 2.2GHz MSK transmitter with a transmission rate of 927.5kb/s. A block diagram of a conventional fractional-N synthesizer is shown in Fig. 19.9.1. The information extracted from the phase detector is inherently analog in nature since the phase information is not synchronized to either the reference clock or the divided down VCO clock and is not quantized. Although conventional XOR and tri-state phase detectors utilize digital building blocks, a charge pump and filter are required to extract useful phase-difference information. Recently, a time-to-digital converter (TDC) is reported that uses multiple flip-flops and unit delays (in practice inverters) to quantize the time difference between the edges of the reference and feedback clock [3]. However, with this approach the resolution and linearity are dependent on the speed and matching of the unit delay elements, and hence inherently process dependent.