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Bitonic st-Orderings for Upward Planar Graphs: The Variable Embedding Setting

机译:向上平面图的BitOnic St订单:变量嵌入设置

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Bitonic si-orderings for si-planar graphs were recently introduced as a method to cope with several graph drawing problems. Notably, they have been used to obtain the best-known upper bound on the number of bends for upward planar polyline drawings with at most one bend per edge. For an si-planar graph that does not admit a bitonic si-ordering, one may split certain edges such that for the resulting graph such an ordering exists. Since each split is interpreted as a bend, one is usually interested in splitting as few edges as possible. While this optimization problem admits a linear-time algorithm in the fixed embedding setting, it remains open in the variable embedding setting. We close this gap in the literature by providing a linear-time algorithm that optimizes over all embeddings of the input si-planar graph. The best-known lower bound on the number of required splits of an si-planar graph with n vertices is n-3. However, it is possible to compute a bitonic si-ordering without any split for the si-planar graph obtained by reversing the orientation of all edges. In terms of upward planar polyline drawings, the former translates into n-3 bends, while the latter into no bends. We show that this idea cannot always be exploited by describing an si-planar graph that needs at least n-5 splits in both orientations.
机译:最近引入了SI-Planar图形的Bitonic Si订购作为应对几个图形绘制问题的方法。值得注意的是,它们已被用来获得最佳已知的上限,以获得向上平面折线图的弯曲数量,每个边缘最多一个弯曲。对于不承认的Si平面图,该图不承认不关机Si订购,可以分割某些边缘,使得对于所得到的图形存在这种排序。由于每个拆分被解释为弯曲,因此一个人通常感兴趣地分配尽可能少的边缘。虽然此优化问题承认固定嵌入设置中的线性时间算法,但它在可变嵌入设置中保持打开。通过提供一种线性时间算法,在文献中缩小了这种差距,该时间算法优化了输入Si平面图的所有嵌入物。具有n个顶点的Si平面图的所需分裂数的最着名的下限为N-3。然而,可以计算通过反转所有边缘的方向而获得的Si-Paralar图表的BitOnic Si订购而没有任何分裂。就向上平面折线图而言,前者转化为N-3弯曲,而后者将没有弯曲。我们表明,不能始终通过描述在两个方向上需要至少n-5分裂的SI平面图来利用这种想法。

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