The design of higher-order reference voltage generation circuits for single-ended memory interfaces

摘要

As the efforts to increase the data rate of single-ended signaling continues, the design of reference voltage generation circuit will likely become more challenging due to the uncorrelated supply-induced noise in particular and external and internal noise in general between signal input and the reference voltage. This is because the receiver of the single-ended interface relies on a reference voltage to reliably discriminate between logic high and low levels at the receiver input. This paper introduces the design of reference voltage generation circuits with the ability to track low and high frequency changes in power supply levels using high order networks. The advantage of the proposed method is demonstrated using measurement and simulation results of a high-speed system based on pseudo open drain signaling running at data rate of 12.8 Gbps.