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Embedded Die Substrates for Power Applications

机译:用于电源应用的嵌入式管芯基板

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Historically, power die like MOSFETs have been packaged on lead frames using wire bonds asinterconnects. To facilitate current carrying requirements, thick wires and sometimes also clips were used, to handlethe total electrical and thermal conductivity requirements. As die are being thinned, it has become possible to takeadvantage of new electrical designs and locate source and drain on opposite sides of the die. Such die can now beeasily packaged by embedding the power die in organic substrates. The die is bonded on a Cu pad and covered byprepreg and copper foil during lamination. Source, drain and gate pads are accessed from the top side with laser viasand filled with plated copper. Finally, the top side is patterned and protected with solder mask. Electrical andthermal modeling data can demonstrate the performance efficiency while reducing the form factor in accordancewith the miniaturization requirements of mobile applications. Aside from single die packages, more advancedpackages can be built containing multiple power die and controller die. The basic process flow remains the samebut does require some adaptation. If so desired, additional components may be assembled on top of the embeddeddie package leading to further integration and miniaturization.
机译:从历史上看,功率管之类的MOSFET都是使用引线键合封装在引线框架上的。 互连。为了满足载流要求,使用了粗电线,有时还使用了夹子来处理 总的电导率和热导率要求。随着模具的变薄,有可能采取 新电气设计的优势,并将源极和漏极放置在芯片的相对侧。这样的死现在可以 通过将电源管芯嵌入有机基板中,可以轻松进行封装。芯片被粘结在铜垫上并被覆盖 层压过程中的预浸料和铜箔。通过激光过孔从顶部访问源极,漏极和栅极焊盘 并填充镀铜。最后,对顶面进行构图并用阻焊剂进行保护。电气和 热建模数据可以证明性能效率,同时减小尺寸因数 符合移动应用的小型化要求。除了单芯片封装,更高级 可以构建包含多个电源芯片和控制器芯片的封装。基本流程保持不变 但确实需要一些调整。如果需要,可以在嵌入式组件的顶部组装其他组件。 芯片封装导致进一步的集成和小型化。

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