A Performance and Functional Assertion-Based Verification Methodology at Transaction-Level

摘要

In this paper, we present an assertion-based verification methodology for system-level design. Transaction-level concepts are integrated with an assertion language to introduce a useful, effective and familiar assertion description language. Our assertion verification language is capable of specifying system-level assertions for validating performance as well as functional properties. Proper-ties can be verified using offline simulation trace analysis. C++ trace checkers are automatically generated to validate particular simulation runs or to analyze their performance characteristic(s). Using a JPEG decoder as a case study, we demonstrate that the assertion-based verification is highly useful for both functional and performance system-level verification.