Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit

摘要

In this paper, we have modified a low-voltage, low- power V_T (Threshold Voltage) extractor circuit, and by doing this we have obtained results with greater accuracy. At the same time, the output generated from this circuit is found to be robust enough against supply voltage variations. This scheme is based on the most popular extraction algorithm which essentially starts with I_d versus V_(GS) characteristics of any MOS transistor operating in saturation. Here the V_T extractor block is followed by an offset generator and a feedback block. Now, for the purpose of modification, we have mainly changed the architecture of the offset generator block, keeping rest of the basic blocks unaltered. While doing this we have achieved more accurate results at low supply voltage ranging from 1.2 to 1.8V. In this range, for almost all the cases we found results with excellent accuracy. Whereas, considering the worst case scenario, the maximum deviation from the SPICE-V_T value is found to be only 2.9%. Low power consumption, self-compensation for any second-order effect etc. are the key features for this modified architecture. The paper describes the V_T extraction scheme, as well as, illustrates the techniques and circuit architecture required for the purpose. The results are supported by SPICE simulations.