Voltage Controlled Delay Line Applied with Memristor in Delay Locked Loop

摘要

In this work, one of memristor characteristic; the varying resistance is applied in CMOS integrated circuits alongside the transistors. Due to memristor small size, by merging memristor and CMOS circuit elements can probably save up area consumption and thus overcome scale limitation problem. In this paper, a delay locked loop has been designed using voltage controlled delay line that was used together with a memristor. By adjusting the resistance of memristor, it was possible to control the bias voltage to get different delays of a single unit delay. In regards to whole DLL designs, we choose phase-frequency-detector (PFD) for phase detector and charge pump with capacitor for the loop filter. The designs are explained including its operation method and considerations on speed and power consumption. Finally, the simulations result of the DLL with varying resistance of memristor will also be discussed. The DLL is designed using 0.18μm process.