System Architecture and FPGA-lmplementation of the SSC Local Dimming Processor for an Edge-Lit Serial TV

摘要

We present an efficient hardware implementation of our local dimming processor which consists of a preprocessor (Condenser), the Sorted Sector Covering (SSC) algorithm and a postprocessor (Pixel Compensation) in a low-cost FPGA. The system runs in a typical 40" Full-HD TV set with edge- LED. An equivalent visual quality like the undimmed version has been achieved, while the power consumption for the BLU with four LED units is reduced by 21%. In case of tolerating limited clipping artifacts, the power consumption can even be reduced by 46%.