Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10–30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred to as interposer approach using ultra-thin glass or silicon with ultra-high I/O density interposers, which does not require TSVs in the logic IC in the 3D stack. This paper presents a comparative study, based on electrical modeling of the logic-to-memory signal path, in various current and emerging package configurations for use in smart mobile devices. Frequency and time domain analysis for each of these scenarios is performed using both chip and package-level models with varying interconnection dimensions. Simulated eye diagrams for the complete data paths in the thin glass interposer approach demonstrated more than 3 Gbps/pin data rate, similar to 3D ICs.
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