首页> 外文会议>61st Electronic Components Technology Conference, 2011 >Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization
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Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

机译:开发具有30μm节距的无铅焊料微凸点的3DIC芯片堆叠的无助焊剂晶圆上键合工艺和可靠性表征

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3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2-- at an ambient temperature of 150°C.
机译:3D IC集成可以通过使用诸如片上芯片,晶片上芯片和晶片上晶圆集成之类的方法来完成。芯片级芯片方案在组装过程中显示出高灵活性和高成品率的优点。然而,低的制造产量一直是主要问题。当与芯片上芯片集成相比时,晶圆上晶圆可以提供更高的制造吞吐量,但是其总良率将受到累积良率的限制。同样,好的芯片被迫粘合到坏的芯片上。因此,晶圆上芯片集成的发展可能是3D芯片堆叠的更好方案。在这项研究中,演示了采用30μm节距的无铅焊料微凸点互连的高产量,无助焊剂的晶片上键合工艺,并评估了微接头的可靠性。本研究中采用的测试芯片具有3000多个微凸点,直径为18μm,间距为30μm。在测试芯片和200mm晶圆的凸块冶金(UBM)下,将Sn2.5Ag焊料材料电镀到Cu / Ni上。为了实现无助焊剂晶圆上键合的目的,将等离子体预处理应用于测试芯片和键合晶圆。还进行了具有间隙控制能力的热压粘合方法。在这项工作中,已经完成了CoW收率超过90%的无助焊剂热压粘合。发现锡厚度的因素明显影响CoW产率。通过优化的等离子体处理参数和键合条件,可以在不使用助焊剂的情况下获得微凸点的良好对准和牢固连接。可靠性测试结果表明,在机械评价下,底部填充胶的引入可以明显提高微接头的可靠性。此外,与标准倒装芯片凸点相比,焊料微凸点接头在5×10 −4 A / cm 2 - -- 在150°C的环境温度下。

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