On gated diodes for ESD protection in bulk FinFET CMOS technology

摘要

The transient behavior of bulk FinFET gated diodes is investigated under ESD conditions. Series diodes are studied in circuit configuration to evaluate their effectiveness as local clamp or traditional dual-diode ESD protection solution. An optimal diode layout configuration is proposed, considering thermal properties, area footprint, capacitive loading and voltage clamping capability.