Origin of It2 drop depending on process and layout with fully silicided ggMOS

摘要

Source-drain process optimization and a diffusion layout technique enable reduction of the snapback voltage (Vt1). Lowering Vt1 of the fully silicided ggMOS enabled low on-resistance and a higher failure current (It2) combined stably in multi-finger turn-on operation. Moreover, to meet both hot-carrier reliability and the ESD requirement, lightly doped drain (LDD) process was obtained.