首页> 外文会议>2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference >Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump
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Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump

机译:预先形成的IMC层对带有焊料覆盖的Cu柱凸点的外围超细间距C2倒装芯片互连电迁移的影响

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The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance incre--ase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.
机译:研究并讨论了80μm间距C2(芯片连接)互连的电迁移(EM)行为[1,2,3]。 C2是一种低成本的外围超细间距倒装芯片互连技术,其基于焊料覆盖的Cu柱状凸点。铜柱凸块形成在引线键合(WB)技术中常用的Al焊盘上。因此,它可以最大程度地利用现有的基础架构。由于C2凸块通过免清洗回流通过有机衬底上的OSP表面处理过的Cu焊盘连接,因此具有很高的产量,并且与SMT(表面贴装技术)兼容。由于管芯和基板之间的空间由Cu柱高度决定,因此不需要进行焊料凸点的塌陷控制。另外,也不需要在基板上进行预焊。对于需要精细间距结构的系统来说,这是一种理想的技术。已经进行了各种可靠性测试,包括C2技术的热循环测试和热湿度偏差测试。但是,针对该技术针对EM故障的可靠性仅进行了很少的研究。在此报告中,EM测试是在80μm节距的C2倒装芯片互连上进行的。测试了两种不同焊料材料的互连:Sn / 2.5Ag和Sn100%。研究了Ni阻挡层对Cu柱的影响以及预先形成的金属间化合物(IMC)层对EM测试的影响。在125–170°C下,测试车辆的EM测试条件为7–10 kA / cm 2 。铜柱高度为45μm,焊料高度为25μm。预成型的IMC的老化过程在150°C下为2,000小时。在测试之后对样品的分析表明,Cu柱解离仅在电子流动方向上发生。但是,未检测到IMC层生长的极性依赖性。具有预先形成的IMC层的C2测试车辆没有明显的电阻增加。 -- 在测试过程中。而且,对于这些测试载具,从管芯上的Cu柱或从基板上的Cu垫都未观察到Cu原子的消耗。具有Ni阻挡层的柱的Cu柱解离到焊料中的数量要少于不含Ni阻挡层的柱。结果表明,预先形成的IMC层的形成和Ni阻挡层的插入对于防止Cu原子解离到焊料中是有效的。本研究表明了一种潜在的方式来形成抵抗电磁破坏的铜柱接头。

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