Design of a CMOS A2I data converter: Theory, architecture and implementation

摘要

We present the design of an analog-to-information (A2I) converter consisting of parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The architecture employs a reconfigurable analog front-end that modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. This front-end is combined with a digital controller which generates the chipping sequences and processes the digitized samples. The result is a highly versatile architecture that is mapped efficiently on a single CMOS chip.