Design constraint of fine grain supply voltage control LSI

摘要

A supply voltage control technique for realizing low power LSI is utilized not only for general purpose processors, but also for custom ASIC thanks to advanced LSI design environments. Fine grain supply voltage control in time domain in power gating and DVFS scheme are seen as promising techniques to reduce power consumption. However, they require additional energy consumption for control themselves. In this paper, we discuss energy consumption including this overhead using simple circuit model and make it clear that charging energy of power supply line limits the minimum sleep duration or cycles as design constraint.