A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation

摘要

This paper describes an integrated SRAM standby power reduction design in a 40nm low power process. It features a closed-loop array leakage control with floating bitlines, reducing 46% of leakage current. It relies on self-refreshing virtual VDD clocked by a PVT-compensated SRAM worst-case data retention sensor. The concept is implemented in a 256kbit SRAM with a 0.242µm² 6T cell.