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A 484-µm2 21-GHz LC-VCO beneath a Stacked-Spiral Inductor

机译:层叠螺旋电感器下方的484-μm 2 21 GHz LC-VCO

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This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though a LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed beneath the inductor. The VCO is implemented by a 65-nm CMOS process, and the chip area is only 484 µm2. This VCO achieves a phase noise of −89.4 dBc/Hz@1MHz, power consumption of 1.92mW, and FOMA of 206 dBc/Hz.
机译:本文提出了一种超紧凑型LC-VCO。由于CMOS数字电路的提速,环形振荡器的抖动已成为一个关键问题。即使LC-VCO具有更好的相位噪声,片上电感器的布局尺寸也作为时钟发生器是一个问题。因此,提出的LC-VCO由一个非常紧凑的叠层螺旋电感器和放置在电感器下方的有源组件组成。 VCO采用65纳米CMOS工艺实现,芯片面积仅为484 µm 2 。该VCO的相位噪声为−89.4 dBc / Hz @ 1MHz,功耗为1.92mW,FOMA为206 dBc / Hz。

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