Resonant clocking is an emerging effective method for reducing power consumption in the clock distribution network. In this technique a resonant (sinusoidal) clock replaces the traditional square wave clock signal. In this paper we combine the emerging resonant clocking technique with the well known dual-edge triggering scheme to enable further power reduction in the clock tree. We propose dual-edge triggering in three pulsed flip-flops that operate with a sinusoidal clock signal; namely: the Static Differential Energy Recovery (SDER) flip-flop, the Differential Conditional Capturing Energy Recovery (DCCER) flip-flop, and the Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop. The proposed dual-edge flip-flops were tested using STMicroelectronics 90nm process technology. Simulation results show the correct operation of the dual-edge triggered flip-flop at a frequency of 250MHz with throughput of 500 MHz.
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