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Soft error rate determination for nanoscale sequential logic

机译:纳米级顺序逻辑的软错误率确定

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We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse width. We extend the analysis to sequential logic and latches and calculate the failures in time (FIT) rate. The analysis is developed for the available background neutron flux data, which is experimentally determined. This, along with the device characteristics, gives the induced pulse parameters. A gate-level algorithm propagates the pulse parameters through logic gates. This algorithm correctly models the logic masking of error pulses. We introduce the concept of latching window that accurately models the temporal masking by sequential elements and present an algorithm for SER analysis of sequential logic.
机译:我们通过使用两个参数(脉冲宽度的出现频率和概率密度函数)对感应误差脉冲进行建模来分析中子感应软误差率(SER)。我们将分析扩展到顺序逻辑和锁存器,并计算时间故障率(FIT)。该分析是针对可用的背景中子通量数据开发的,该数据是通过实验确定的。这与设备特性一起给出了感应脉冲参数。门级算法通过逻辑门传播脉冲参数。该算法正确地建模了误差脉冲的逻辑屏蔽。我们介绍了锁存窗口的概念,它可以精确地模拟顺序元素的时间掩蔽,并提出一种用于顺序逻辑SER分析的算法。

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