Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis

摘要

A novel high-level synthesis (HLS) technique to improve the clock frequency is presented. Our technique aims at the reduction of the clock period by eliminating interconnections, specifically multiplexers (MUXs). MUXs are generally inserted before shared functional units and shared registers. However, MUXs are also inserted before a register even if the register is not shared by multiple variables at all. This paper proposes aggressive register unsharing to remove these MUXs and to improve the clock frequency. Our proposed technique employs static single assignment (SSA) transformation, which is mainly used as a compiler intermediate representation, to behavioral descriptions. This technique is widely applicable to a variety of HLS tools because it is completely independent of the HLS tools. We have developed a complete synthesis framework using an open source compiler, COINS, for SSA transformation, a commercial HLS tool, and an in-house converter which refines a COINS-generated code into one compatible with the HLS tool. Six sets of experiments showed the clock frequency improvement by up to 61.5% and on average 26.7% with the acceptable overhead on the circuit area by on average 10.6%.