A Research and Design of Decimal Floating Multiplier Based on FPGA

摘要

This article is based on the new standard, uses the FPGA device opening, adopts FPGA technique of EDA to build 64 bits decimal floating multiplier model. And in this article, we mainly use DPD codec and BCD new codec and Signed-Digit radix-5 to process coefficient. At last, we use Decimal 32:2 CSA algorithm to process partial product. This effectively increases the computing speed and accuracy. As the new standard revision and widespread application of the decimal floating-point multiplication operations, this design has a certain practical significance in the medical and financial sectors, as well as image processing technology.