High-speed Parallel 32×32-b Multiplier Using a Radix-16 Booth Encoder

摘要

A 32 × 32-b high-speed parallel multiplier is proposed in this paper. The new multiplier uses a Radix-16 Booth Encoder, uses a mixed compressed tree constituted by 4-2 and 5-2 compressor and an improved 64-bit carry-look ahead adder (CLA) which combines the characteristics of CSS and CLA. The test result shows that, compared with iterative multiplier, this multiplier has some improvement on performance.