In complex SoC designs verification consumes more than half of the overall design effort. Design reuse is a critical element in closing the SoC design gap, but it is not enough. A generic core-based architecture for circuits that require high volume data transfer control was designed. After some experience in reusing the architecture, a key improvement has recently been undertaken: a reusable simulation platform. The complexity of architectural verification and performance analysis has been greatly alleviated by means of a monitor module that processes all the events on the SoC and an Architecture Specific Graphical User Interface (ASGUI) that shows all the data transfers while simulation is running. The generation of bitrate and latency statistics is fully automated.
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