Architecture for Context-driven Packet Payload Processing Engine

摘要

Link speeds have been increasing dramatically over the past few years, and packet analysis has broadened from conventional header search to search of predefined strings in packet payload. With increasing traffic speed, conventional software based packet processing techniques have difficulty in processing payloads without burdening system performance. This has led researchers to look for hardware-based alternatives for packet processing. One such technique that uses a specialized structure called a "Shared-resource Bloom filter" to isolate potentially suspicious packets is described in this paper. An important part of this technique is the hardware implementation of analyzer unit, which eliminates the false positives coming from the shared resource Bloom filter. Results of a prototype implementation of this technique using Xilinx XC2VP20 FPGA are presented.