Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation

摘要

As the complexity of chip designs increase, simulation time also increases. Unit and variable delay simulation takes the most simulation time in IC design process; however, parallel processing performs inefficiently due to large amount of synchronization, In this paper, techniques to reduce the number of synchronization points in synchronous designs are proposed, and a partitioner to partition designs along flip-flop boundaries is also proposed so that these techniques can be employed on real designs.