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A 90nm Copper CMP Process with Low Defectivity Using Optimized Copper and Barrier Removal Slurries

机译:采用优化的铜和势垒去除浆料的低缺陷的90nm铜CMP工艺

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As outlined in the International Technology Roadmap for Semiconductors (ITRS), the stringent requirements for Cu interconnects has become more aggressive as the device size shrinks, wafers increase in diameter from 200mm to 300mm and the underlying dielectric's k value gets lower, not to mention the increasingly complex integration schemes employing various barrier, dielectric and cap/stop layers. Additionally, CMP defects that could be ignored in the past are becoming critical as the industry is forced to change its manufacturing practices to attain maximum yield with multilevel copper interconnects. Copper CMP processes are more complex and involve more than one polish step using different pads and slurries. For copper/TEOS wafer processes, and the next-generation Cu/low-k CMP processes, the slurry and its chemistry play a major role in controlling defects and various wafer metric parameters such as dishing, erosion, selectivity, non-uniformity, etc. Robust slurries must have the ability to repeatedly produce wafers with minimal defects and stable wafer metrics. This presentation focuses on minimizing various types of CMP defects on copper wafers through the proper selection of slurry chemistry, process optimization and slurry handling. A variety of wafers with different metal layers and test patterns were polished on an AMAT Mirra~R tool with Rodel~R EPL2361 for first step copper polish and Rodel~R CUS1351 for the barrier polish. It is evident that for a slurry/pad combination, process tuning of various equipment parameters helped minimize the CMP-related defects. Slurry handling, such as proper filtration methodology, slurry flow rate, pad rinse, and pad cleaning, along with properly tuned equipment parameters, resulted in further reduction of the amount and severity of the CMP-related defects. Since most of the CMP defects are preferentially positioned on the copper surface, the first-step copper process plays a significant role in the final defectivity of the wafer. It is very difficult to minimize defect levels if the first-step process introduces significant damage to copper lines or large surface areas such as bond pads. Since the second-step barrier polish process is typically designed to remove minimal copper and maintain the total metal thickness in the damascene structures, an optimized first-step copper removal process that dramatically lowers overall defect density definitely improves final defect levels after second-step barrier CMP.
机译:正如《国际半导体技术路线图》(ITRS)所述,随着器件尺寸的缩小,晶圆直径从200mm增加到300mm以及底层电介质的k值降低,对Cu互连的严格要求变得更加严格。使用各种势垒层,电介质层和盖帽/停止层的集成方案日趋复杂。此外,随着行业被迫改变其制造方式以利用多层铜互连实现最大产量,过去可以忽略的CMP缺陷变得越来越重要。铜CMP工艺更加复杂,并且使用不同的抛光垫和浆料进行一个以上的抛光步骤。对于铜/ TEOS晶圆工艺以及下一代Cu / low-k CMP工艺,浆料及其化学成分在控制缺陷和各种晶圆度量参数(例如凹陷,腐蚀,选择性,不均匀性等)方面起着重要作用。 。坚固的浆料必须具有重复生产具有最小缺陷和稳定晶圆规格的晶圆的能力。该演讲将重点讨论通过浆化学,工艺优化和泥浆处理的正确选择最大限度地减少各类铜晶圆CMP缺陷。在AMATMirra®R工具上进行抛光,将具有不同金属层和测试图案的各种晶圆抛光,其中Rodel®R EPL2361进行第一步铜抛光,而Rodel®RCUS1351进行阻挡层抛光。显然,对于浆料/抛光垫组合,各种设备参数的工艺调整有助于最大程度地减少与CMP相关的缺陷。浆料处理(例如正确的过滤方法,浆料流速,垫冲洗和垫清洁)以及适当调整的设备参数可进一步降低与CMP相关的缺陷的数量和严重性。由于大多数CMP缺陷优先位于铜表面,因此第一步铜工艺在晶片的最终缺陷率中起着重要作用。如果第一步工艺会对铜线或较大的表面积(例如焊盘)造成严重损坏,则将缺陷水平降至最低非常困难。由于第二步势垒抛光工艺通常设计用于去除最小的铜并保持镶嵌结构中的总金属厚度,因此优化的第一步铜去除工艺可显着降低总体缺陷密度,从而肯定会改善第二步势垒后的最终缺陷水平CMP。

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