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Run-time energy estimation in system-on-a-chip designs

机译:片上系统设计中的运行时能量估计

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In this paper, a co-processor for run-time energy estimation in system-on-a-chip designs is proposed. The estimation process is done by using power macro-models, thus making analogue measurement equipment obsolete to the software engineer once the system-on-a-chip (SOC) design is characterized. Compared to sampling-based profiling systems [17], the performance overhead of energy profiling is less, because the energy estimation is done completely parallel to the functional units residing on the SOC. The proposed methodology can be used for run-time power optimization and in-system energy profiling. The co-processor was evaluated on a SOC for MPEG layer III audio decoding and the experimental results show a maximum relative error of 5%.
机译:本文提出了一种用于单芯片系统设计中运行时能量估计的协处理器。估计过程是通过使用功率宏模型完成的,因此一旦表征了片上系统(SOC)设计,就使软件工程师无法使用模拟测量设备。与基于采样的分析系统相比,[17]能量分析的性能开销较小,因为能量估算是完全与SOC上的功能单元并行完成的。所提出的方法可以用于运行时功率优化和系统内能量分析。协处理器在SOC上进行了MPEG层III音频解码的评估,实验结果显示最大相对误差<5%。

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