Parallel pipleine networking and signal processing with field programmable gate arrays (FPGAs) and VCSEL-MSM smart pixels

摘要

We present a networking and singal processing architecture called Transpar-TR (Translucent Smart Pixel Array-Token-Ring) that utilizes msart pixel technology to perform 2-D parallel optical data transfer between digital processing nodes. Transpar-TR moves data through the network in the form of 3-D packets (2-D spatial and 1-D time). By utilizing many spatial parallel channels, Transpar-TR can achieve high throughput, low latency communication between nodes, even with each channel operating at moderate data rates. The 2-D array of optical channels is created by an array of smart pixels, each with an optical input and optical output. Each smart pixel consists of two sections, an optical network interface and ALU-based processor with local memory. The optical network interface is responsible for transmitting and receiving optical data packets using a lotted token ring network protocol. The smart pixel arrays operates as a single-instruction multiple-data (SIMD) processor when processing data. The Transpar-TR network, consisting of networked smart pixel arrays, can perorm pipelined parallel processing very efficiently on 2-D data structures such as images and video. This paper discusses the Transpar-TR implementation in which each node is the printed circuit board integration of a VCSEL-MS chip, a transimpendance receiver array chip and an FPGA chip.